library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity register_update is
	Port(Input     : in  STD_LOGIC_VECTOR(7 downto 0);
		 RegCtrl   : in  STD_LOGIC_VECTOR(1 downto 0);
		 next_RegA : out STD_LOGIC_VECTOR(7 downto 0);
		 next_RegB : out STD_LOGIC_VECTOR(7 downto 0)
	);
	signal RegA : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
	signal RegB : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
end register_update;

architecture Behavioral of register_update is
begin
	Update : process(RegCtrl, Input, RegA, RegB) is
	begin
		case RegCtrl is
			when "01" =>
				next_RegA <= Input;
				RegA      <= Input;
			when "10" =>
				next_RegB <= Input;
				RegA      <= Input;
			when others =>
				next_RegA <= RegA;
				next_RegB <= RegB;
		end case;

	end process Update;

end Behavioral;

